1. Field of the Invention
This invention relates to high speed programmable delay line elements that include gallium arsenide static random access memories (SRAM) circuits and, more particularly, to programmable delay line static random access memories that provide a variable time delay and still more particularly to the radio frequency use of such circuits.
2. BRIEF DESCRIPTION OF THE PRIOR ART
Digital radio frequency memories (DRFM) are utilized in signal acquisition and processing systems which combine analog and digital components to record samples of received radio frequency signals and process the samples in real time. In the conventional DRFM architecture using silicon components high sampling rates of radio frequency signals can be attained with relatively slow memories by demultiplexing the sample data stream into a large number of parallel paths. However, the component count and interconnection complexity rapidly become excessive at the higher sampling rates. At rates on the order of 1 GHz noise is also a problem. With sufficient demultiplexing, the sampling rate of this architecture should be limited by the maximum operating speed of the demultiplexer and multiplexer components and interconnect problems.
In one radio frequency repeater system, a GHz DRFM using the above described architecture including, slow silicon memories and GaAs shift registers for demultiplexing and multiplexing has been reported by B. M. Gilbert, D. J. Schwab, L. M. Pastuszyn, A. Firstenberg and R. H. Evans in an article entitled "Design and Fabrication of a Digital RF Memory Using Custom Designed GaAs Integrated Circuits," IEEE GaAs Integrated Circuit Symposium Technical Digest, Nov. 1985, pages 173 to 176. The system described in this article is extremely complex, requiring an eight layer wire wrap board with more than 100 ECL chips and a twelve layer rf printed wiring board (PWB) for the GaAs components.
It initially appears that the use of all GaAs components in a traditional radio frequency repeater architecture, as described in the above noted prior art in conjunction with silicon devices, should result in a simpler system, since significantly less demultiplexing and multiplexing is required to match the much faster GaAs memories to the input and output data streams. While the narrower demultiplexer and multiplexer components do result in some simplification, such simplification is effectively offset by the complexities that arise from the proportionately higher speed data and address and control lines. High speed buffer networks and fanout trees must maintain critical timing relationships with respect to the memory address and control lines. Additionally, off-chip propagation delays require precise control. Thus, critical timing relationships must be provided and have required the use of tree circuits to provide individual timing signals from a timing source directly to each chip with appropriate built in circuit delays.
This critical relationship is extremely difficult to achieve in higher speed circuit design. Thus, little or no overall advantage is expected from an all GaAs traditional repeater architecture system over the GaAs demultiplexed system with slow silicon memories.